• DocumentCode
    1280965
  • Title

    High-level test synthesis based on controller redefinition

  • Author

    Fernández, V. ; Sánchez, P.

  • Author_Institution
    Microelectron. Eng. Group, Cantabria Univ., Santander, Spain
  • Volume
    33
  • Issue
    19
  • fYear
    1997
  • fDate
    9/11/1997 12:00:00 AM
  • Firstpage
    1596
  • Lastpage
    1597
  • Abstract
    A novel approach is proposed for the high-level synthesis of data-dominated circuits. The functionality of the controller is redefined in order to improve the testability of the final circuit. The data path is left untouched. Test results are obtained at gate-level, after the RT synthesis process, with a sequential test generation package, HITEC
  • Keywords
    design for testability; high level synthesis; logic testing; sequential circuits; HITEC; RT synthesis process; controller functionality; controller redefinition; data-dominated circuits; gate-level test results; high-level test synthesis; sequential test generation package; testability;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19971114
  • Filename
    629576
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1280965