Title :
High-level test synthesis based on controller redefinition
Author :
Fernández, V. ; Sánchez, P.
Author_Institution :
Microelectron. Eng. Group, Cantabria Univ., Santander, Spain
fDate :
9/11/1997 12:00:00 AM
Abstract :
A novel approach is proposed for the high-level synthesis of data-dominated circuits. The functionality of the controller is redefined in order to improve the testability of the final circuit. The data path is left untouched. Test results are obtained at gate-level, after the RT synthesis process, with a sequential test generation package, HITEC
Keywords :
design for testability; high level synthesis; logic testing; sequential circuits; HITEC; RT synthesis process; controller functionality; controller redefinition; data-dominated circuits; gate-level test results; high-level test synthesis; sequential test generation package; testability;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19971114
