DocumentCode
1280971
Title
Design of low-error fixed-width multiplier for DSP applications
Author
Jou, Jer Min ; Kuang, Shiann Rong
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
33
Issue
19
fYear
1997
fDate
9/11/1997 12:00:00 AM
Firstpage
1597
Lastpage
1598
Abstract
A low-error design of the fixed-width parallel multiplier for digital signal processing (DSF) applications is proposed. Applying two n bit inputs, it generates the n bit, instead of 2n bit, product with lower relative product errors, but uses only about half the area of a standard parallel multiplier. These features make it very suitable for use in many DSP applications such as arithmetic coding, wavelet transformation, digital filtering
Keywords
digital signal processing chips; multiplying circuits; DSP; arithmetic coding; digital filtering; digital signal processing; fixed-width parallel multiplier; low-error design; wavelet transformation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19971087
Filename
629577
Link To Document