Designs of All Digital Phase Locked Loop

Author

Singhal, Achintya ; Madhu, Charu ; Kumar, Vipin

Author_Institution

Dept. of Electron. & Commun., Univ. Inst. of Eng. & Technol., Chandigarh, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

5

Abstract

Phase Locked Loop (PLL) is a feedback system that is configured as frequency multipliers, tracking generators, demodulators and clock recovery circuits. Today the most challenging requirement engineers´ face is design of fast locking PLL with low jitter. Many analog techniques are proposed to fulfill the demand but they result in increasing complexity of design and long lock in time. In this paper, review of advantages of an All-Digital phase locked loop (ADPLL) over an analog phase locked loop (APLL) in terms of stability, programmability is studied. Various approaches to design the blocks of ADPLL till now adopted are presented in this paper.

Keywords

demodulators; digital phase locked loops; jitter; synchronisation; ADPLL; APLL; all-digital phase locked loop; analog phase locked loop; analog techniques; clock recovery circuits; demodulators; fast locking PLL; feedback system; frequency multipliers; jitter; tracking generators; Detectors; Jitter; Mathematical model; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators; Phase Locked Loop (PLL); all digital phase locked loop (ADPLL); analog phase locked loop (APLL);

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering and Computational Sciences (RAECS), 2014 Recent Advances in

Conference_Location

Chandigarh

Print_ISBN

978-1-4799-2290-1

Type

conf

DOI

10.1109/RAECS.2014.6799523

Filename

6799523