• DocumentCode
    1281079
  • Title

    CMOS inverter maximum frequency of operation due to digital signal degradation

  • Author

    Juan-Chico, J. ; Bellido, M.J. ; Acosta, A. ; Barriga, A. ; Valencia, M.

  • Author_Institution
    Inst. de Microelectronica de Sevilla, Spain
  • Volume
    33
  • Issue
    19
  • fYear
    1997
  • fDate
    9/11/1997 12:00:00 AM
  • Firstpage
    1619
  • Lastpage
    1621
  • Abstract
    An operation frequency limit for the CMOS inverter is presented, based on delay degradation. This allows treatment of the problem from a purely logical viewpoint. Classical calculations are shown to lead to large over-estimations
  • Keywords
    CMOS logic circuits; delays; logic design; logic gates; CMOS inverter; delay degradation; digital signal degradation; maximum operation frequency; operation frequency limit;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19971102
  • Filename
    629593
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1281079