Title :
High-bandwidth CMOS test buffer with very small input capacitance
Author :
Duque-Carrillo, J.F. ; Perez-Aloe, R.
Author_Institution :
Dept. de Electronca e Ing. Electronmecanica, Extremadura Univ., Badajoz, Spain
Abstract :
An analogue CMOS buffer configuration, which eliminates the tradeoff between high bandwidth and very low input capacitance, has been designed and simulated in a standard 2 mu m process. The circuit shows a total input capacitance less than 50 fF up to 12 MHz and less than 110 fF overall with a 3 dB bandwidth of 20 MHz when driving a 15 pF and 100 k Omega load. The very small input capacitance and high bandwidth make the circuit very suitable for testing internal sensitive nodes in CMOS analog or mixed-mode circuits.
Keywords :
CMOS integrated circuits; buffer circuits; integrated circuit testing; linear integrated circuits; 12 to 20 MHz; 2 micron; 20 MHz; 50 to 110 fF; CMOS test buffer; analogue CMOS buffer configuration; high bandwidth; input capacitance; testing internal sensitive nodes in CMOS;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19901343
