• DocumentCode
    1281403
  • Title

    Scalable processor architecture for Java with explicit thread support

  • Author

    Buchenrieder, K. ; Kress, R. ; Pyttel, A. ; Sedlmeier, A. ; Veith, C.

  • Author_Institution
    Siemens AG, Munich, Germany
  • Volume
    33
  • Issue
    18
  • fYear
    1997
  • fDate
    8/28/1997 12:00:00 AM
  • Firstpage
    1532
  • Lastpage
    1534
  • Abstract
    A scalable processor architecture for multi-threaded JavaTM applications is presented. The proposed architecture consists of multiple application-specific processing elements, each able to execute a single thread at one time. The architecture is evaluated by implementing a portable and scalable Java machine on an FPGA board for demonstration
  • Keywords
    computer architecture; field programmable gate arrays; object-oriented programming; FPGA board; Java; application-specific processing elements; object-oriented multi-threaded language; portable machine; scalable processor architecture; thread support;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19971049
  • Filename
    629640
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1281403