DocumentCode :
1281761
Title :
New Insight Into PBTI Evaluation Method for nMOSFETs With Stacked High- k /IL Gate Dielectric
Author :
Lee, Sang Kyung ; Jo, Minseok ; Sohn, Chang-Woo ; Kang, Chang Yong ; Lee, Jong Chul ; Yoon-Ha Jeong ; Byoung Hun Lee
Author_Institution :
SEMATECH, Austin, TX, USA
Volume :
33
Issue :
11
fYear :
2012
Firstpage :
1517
Lastpage :
1519
Abstract :
In this letter, a strategy to minimize the error in lifetime projections using a positive bias temperature instability (PBTI) test has been proposed. Two distinctly different projection slopes were observed in a plot of time to failure versus oxide electric field. A small slope in the high-field region, which means weaker electric field dependence, led to an underestimation of lifetime. This result was attributed to a filled trap cluster at a specific trap energy level, locally reducing the oxide electric field. Thus, different lifetimes can be projected depending on stress bias. Maintaining a PBTI stress bias range below this trap energy level is recommended for accurate projections.
Keywords :
MOSFET; failure analysis; high-k dielectric thin films; stability; PBTI evaluation method; electric field dependence; failure analysis; filled trap cluster; high-field region; lifetime projection error; nMOSFET; oxide electric field; positive bias temperature instability; specific trap energy level; stacked high-k-IL gate dielectric; stress bias; Electron traps; Hafnium compounds; High K dielectric materials; Logic gates; MOSFETs; Stress; $hbox{HfO}_{2}$; lifetime; nMOSFET; positive bias temperature instability (PBTI); trap cluster;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2012.2211072
Filename :
6296679
Link To Document :
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