DocumentCode
1281788
Title
Algorithm-Enhanced Retention Based on Megabit Array of 
RRAM
Author
Wang, Yan-Liang ; Song, Ya-Li ; Yang, Ling-Ming ; Lin, Yin-Yin ; Huang, Ryan ; Zou, Qin-Tian ; Wu, Jin-Gang
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Volume
33
Issue
10
fYear
2012
Firstpage
1408
Lastpage
1410
Abstract
Robust retention is achieved on 1-Mb CuxSiyO resistive random access memory test chip. The Ron retention fail bits can be effectively improved by enhanced set algorithm. The baking failure rate is less than 9 ppm after baking at 125°C for 1000 h under set algorithm (CC = 25 μA, PA = 2 V, and PD = 100 ns). Ron resistance can be used as retention criterion in production screening whatever the algorithm is. The mechanism of retention enhanced by algorithm is proposed based on the conductive filament model.
Keywords
MIS devices; MOS memory circuits; copper compounds; electric resistance; failure analysis; random-access storage; semiconductor device testing; silicon compounds; CuxSiyO; RRAM; baking failure rate; conductive filament model; current 25 muA; enhanced set algorithm; megabit array-based algorithm-enhanced retention; production screening; resistive random access memory test chip; retention fail bits; robust retention; storage capacity 1 Mbit; temperature 125 degC; time 100 ns; time 1000 h; voltage 2 V; Arrays; Electron devices; Random access memory; Resistance; Robustness; Switches; Memory array; resistive random access memory (RRAM); retention; test chip;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2012.2210991
Filename
6296682
Link To Document