Improved Model-to-Hardware Correlation for Superconductor Integrated Circuits

Superconductor (SC) integrated circuits have several inherent advantages including low power, high speed, and fractional flux quantum sensitivity that can be exploited to achieve discriminating performance for several niche applications in the high-speed computing and radio frequency domain. Despite its several advantages, scaling of SC circuits to higher complexity has been inhibited by the poor circuit yield. One of the critical factors limiting the yield is the poor simulation model to hardware correlation. The current simulation tools for SC circuits such as PSCAN are inadequate to simulate high circuit complexity and do not account for the variations in the fabrication process. To overcome this limitation, we have developed an advanced infrastructure for SC circuit simulation, verification, and model-to-hardware correlation based on the Cadence design suite, particularly using the state-of-the-art Spectre simulator that supports high circuit complexity and Monte Carlo simulations. An improved model-to-hardware correlation will result in several benefits that include enabling circuit scaling to higher complexity. Statistical distributions for critical circuit elements are measured by novel diagnostic circuits that enable measuring multiple instances on a single chip and mimic layout features in actual circuits. Statistical variations are being measured over multiple wafer runs and will be fed into the new simulation infrastructure to achieve better optimization of a complex SC circuit. Furthermore, ring oscillator test circuits for Josephson transmission line have been designed and measured to study the delay per junction as a function of characteristic voltage V_c.