High performance CMOS current comparator design

Author

Palmisano, Giuseppe ; Palumbo, Gaetano

Author_Institution

Dipartimento Elettrico Elettronico e Sistemistico, Catania Univ., Italy

Volume

43

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

785

Lastpage

790

Abstract

The paper describes some design aspects in the implementation of CMOS current comparators. More specifically, techniques for offset and charge-injection compensations are discussed in detail, and some basic topologies for compensated current comparators are presented and compared by SPICE simulations. Moreover, a novel compensated fully differential current comparator is proposed which achieves a very high performance. It provides a sensitivity as low as 20 nA and a switching time better than 30 ns with a 0.5 μA input step current while dissipating 45 μW

Keywords

CMOS analogue integrated circuits; SPICE; circuit analysis computing; compensation; current comparators; digital simulation; integrated circuit design; sensitivity analysis; 30 ns; 45 muW; CMOS current comparator; SPICE simulation; charge-injection compensation; fully differential comparator; input step current; offset compensation; sensitivity; switching time; Circuits; Feedback; Mirrors; Power dissipation; SPICE; Signal processing; Switches; Time factors; Topology; Voltage control;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.553392

Filename

553392