Title :
±0.9 V switched-capacitor CMOS multiplier with rail-to-rail input
Author :
Grech, I. ; Micallef, J. ; Vladimirova, T.
Author_Institution :
Dept. of Microelectron., Malta Univ., Msida, Malta
fDate :
9/30/1999 12:00:00 AM
Abstract :
An analogue, fully differential, switched capacitor CMOS multiplier with rail-to-rail input capability is presented, together with simulation results. The multiplier can operate at a clock frequency of 10 MHz when operated from a ±0.9 V power supply. Special attention has been given to the minimisation of clock feedthrough errors and also to achieve a low common mode voltage error at the output. The latter makes the device suitable for use in correlators with large integration periods
Keywords :
CMOS analogue integrated circuits; analogue multipliers; errors; switched capacitor networks; -0.9 V; 0.9 V; 10 MHz; analogue SC CMOS multiplier; clock feedthrough errors; correlator application; error minimisation; fully differential CMOS multiplier; low common mode voltage error; rail-to-rail input capability; switched-capacitor CMOS multiplier;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991156
