A Novel Single Ended 8T SRAM with improved Noise Margins and stability

Improving the Noise Margin is one of the important challenges in every state of the art SRAM design. Due to the process variations like threshold voltage variations, supply voltage variations etc. in scaled technologies, stable operation of the bit cell is critical to obtain with high yield in low-voltage SRAM. Proposed design enhanced the read stability by using Buffered Read scheme which decouples SRAM cell nodes from the bit-line. It also improves the write ability by dynamic mechanism of cutting off the feedback loop of the inverter pair. Proposed 8T SRAM cell uses a single bit-line scheme to perform the write and read operation. This reduces half of the power dissipation during pre-charging or discharging bit-line as compared to conventional 6T SRAM cell. The simulation results show that the SE 8T SRAM cell achieves 6.5 x Read noise margin, 1.7 x Write-1 ability, and 1.11 x Write-0 ability as compared with conventional 6T SRAM Cell at 0.9V. Read power dissipation and Static power dissipation have also been reduced.