Title :
Fast lock-on time mixed mode DLL with 10 ps jitter
Author :
Han, Seon-Ho ; Lee, Joo-Ho ; Yoo, Hoi-Jun
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
9/30/1999 12:00:00 AM
Abstract :
A fast lock-on time mixed mode delay locked loop (DLL) is proposed to eliminate phase error in two steps. A digital fixed delay line compensates for the initial large phase error and an analogue voltage controlled delay line compensates for the small static phase error, resulting in low jitter. The lock-on time of the DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz
Keywords :
clocks; delay lines; delay lock loops; mixed analogue-digital integrated circuits; timing jitter; 10 ps; 200 MHz; analogue voltage controlled delay line; clock cycles; digital fixed delay line; jitter; lock-on time; mixed mode DLL; static phase error;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991217
