Voltage- and current-based fault simulation for interconnect open defects

This paper describes a highly accurate and efficient fault simulator for interconnect opens in combinational or full-scan digital CMOS circuits. The analog behavior of the wires with interconnect opens is modeled very efficiently in the vicinity of the defect in order to predict what logic levels the fanout gates will interpret and whether a sufficient IDDQ current will be flowing inside the fanout gates. The fault simulation method is based on characterizing the standard cell library with SPICE, using transistor charge equations for the site of the open, using logic simulation for the rest of the circuit, taking four different factors that can affect the voltage of an open into account, and considering the potential oscillation and sequential behavior of interconnect opens. The tool can simulate test vectors for both voltage and current measurements. Simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets are presented