Title :
Cell processing LSIs for 2.4 Gbit/s SDH-based ATM transmission system
Author :
Tatsuno, H. ; Tokura, N. ; Maeda, Yuji ; Kikuchi, Kazuro
Author_Institution :
NTT Transmission Syst. Lab., Kanagawa, Japan
fDate :
7/4/1991 12:00:00 AM
Abstract :
Introduces cell processing large-scale integrated circuits (LSIs) suitable for byte-oriented systems operating at 2.4 Gbit/s. The LSIs are based on a newly proposed cell delineation circuit which uses a pipeline processing technology to realise byte-by-byte shift operations, an error-detect and error-correct circuit and a descrambling circuit. Prototype LSIs, constructed with a super-selfaligned process technology (SST), are tested at up to 3.7 Gbit/s.
Keywords :
digital communication systems; digital signal processing chips; error correction; large scale integration; time division multiplexing; 2.4 Gbit/s; SDH-based ATM transmission system; SST; byte-by-byte shift operations; byte-oriented systems; cell delineation circuit; cell processing LSIs; descrambling circuit; error-correct circuit; error-detect; large-scale integrated circuits; pipeline processing; super-selfaligned process technology;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19910767
