A novel low leakage and high density 5T CMOS SRAM Cell in 45nm technology

Author

Gupta, Rajesh ; Gill, Sandeep Singh ; Kaur, Navjot

Author_Institution

Dept. of Electron. & Commun. Eng., Guru Nanak Dev Eng. Coll., Ludhiana, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

6

Abstract

In this paper a new 5T SRAM cell is proposed with fast performance, high density and low power consumption. The proposed CMOS SRAM cell consumes less power and has less read and write time. It is capable of storing the bits effectively. The novel cell size is 24.37% smaller than the conventional six-transistor SRAM cell using same design rules without any performance degradation. Simulation results show that there is substantial improvement in performance of the proposed cell as regards performance parameters like delay, power consumption and leakage current. The novel configuration has been analyzed using cadence virtuoso tool in 45nm technology node.

Keywords

CMOS integrated circuits; SRAM chips; leakage currents; low-power electronics; CMOS SRAM cell; cadence virtuoso tool; cell size; delay; leakage current; performance parameters; power consumption; size 45 nm; Delays; Leakage currents; Logic gates; Power demand; SRAM cells; Transistors; 45nm technology; 5T configuration; CMOS SRAM cell; Cell delay; Low Leakage cell; Performance analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering and Computational Sciences (RAECS), 2014 Recent Advances in

Conference_Location

Chandigarh

Print_ISBN

978-1-4799-2290-1

Type

conf

DOI

10.1109/RAECS.2014.6799650

Filename

6799650