A novel low leakage and high density 5T CMOS SRAM Cell in 45nm technology

In this paper a new 5T SRAM cell is proposed with fast performance, high density and low power consumption. The proposed CMOS SRAM cell consumes less power and has less read and write time. It is capable of storing the bits effectively. The novel cell size is 24.37% smaller than the conventional six-transistor SRAM cell using same design rules without any performance degradation. Simulation results show that there is substantial improvement in performance of the proposed cell as regards performance parameters like delay, power consumption and leakage current. The novel configuration has been analyzed using cadence virtuoso tool in 45nm technology node.