Development and analysis of C/A code generation of GPS receiver in FPGA and DSP

The Global Navigation Satellite System (GNSS) plays an important role in positioning and navigation applications. The Civilians are widely using GNSS in many applications like safety-life and positioning applications. The Global Positioning Service (GPS) augmentation is to achieve more reliable and accurate navigation solutions. The presently available traditional GNSS receivers are hardware based receivers which are not flexible and cannot be easily upgraded to acquire the signals from other GNSS systems. The aim of this work is to implement and develop a platform that allows developing a GPS software receiver using available signal processing techniques. This allows to test and implement a new algorithm which also permits to upgrade the receiver easily to new signal structures or even other navigation systems. In this paper we developed Coarse/Acquisition (C/A) code generator of GPS receiver and implemented in Virtes-5 FPGA and Blackfin 533 DSP boards by using Xilinx ISE 13.2 and Matlab 2010a respectively. The Agilent logic analyzer 1692-A is integrated with FPGA for accurate timing analysis.