Pipelined implementation of a Hessenberg-based filter structure

In this paper, a pipelined implementation of a Hessenberg-based input balanced realization is derived, which is realized by placing the delay elements in the lower path and the upper path alternately. The proposed pipelined structure is canonical in the sense that no extra delay is needed. For an Nth order filter, the proposed structure requires 5N -1 multipliers, which has two less multipliers than the normalized lattice structure. Two numerical examples are presented to demonstrate the performance of the proposed structure comparing with the other traditional structures.