Title :
Shielding Methodologies in the Presence of Power/Ground Noise
Author :
Köse, Selçuk ; Salman, Emre ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USA
Abstract :
Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line widths, and interconnect driver resistances. Considering the P/G noise, a shield line can degrade rather than enhance signal integrity due to increased P/G noise coupling on the victim line. A 2π RLC interconnect model is used to investigate the effects of both coupling capacitance and mutual inductance on the crosstalk noise. Physical spacing and shield insertion are compared in terms of the coupling noise on the victim line for several technology nodes. Boundary conditions are also provided to determine the effective range of spacing and shield insertion in the presence of P/G noise. Additionally, the effects of technology scaling on P/G noise and shielding efficiency are discussed, and related design tradeoffs are addressed.
Keywords :
crosstalk; integrated circuit design; integrated circuit interconnections; noise; shielding; P-G noise coupling presence; RLC interconnect model; coupling capacitance; crosstalk noise; interconnect driver resistance; line length; line width; mutual inductance; physical spacing; power-ground noise coupling presence; shield insertion; shielding methodology; signal integrity enhancement; Capacitance; Coupling circuits; Crosstalk; Inductance; Integrated circuit interconnections; Integrated circuit noise; Integrated circuit technology; Noise reduction; Semiconductor device noise; Voltage; $dI/dt$ noise; Coupling capacitance; crosstalk noise; crosstalk reduction techniques; interconnect; mutual inductance; power/ground (P/G) noise; shield insertion; spacing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2010.2054119
