Sample-Efficient Regression Trees (SERT) for Semiconductor Yield Loss Analysis

Regression trees have been known to be an effective data mining tool for semiconductor yield analysis. The regression tree is built by iteratively splitting dataset and selecting attributes into a hierarchical tree model. The sample size reduces sharply after few levels of data splitting causing unreliable attribute selection. In contrast, the forward stepwise regression analysis selects critical attributes all the way with the same set of data. Regression analysis is, however, not capable of splitting data into groups with different underlying models. In this research, we propose a sample-efficient regression tree (SERT) approach that combines the forward selection in regression analysis and regression tree methodologies. The proposed approach is shown to be able to fully utilize the dataset´s degree of freedom and build piecewise linear model to capture the attribute effects. Case studies show that SERT is effective in discovering yield-loss causes during the yield ramp-up stage where the sample size available for analysis is relatively small.