DocumentCode
1285114
Title
Completion-detection technique for dynamic logic
Author
Bartlett, V.A. ; Grass, E.
Author_Institution
Dept. of Electron. Syst, Westminster Univ., London, UK
Volume
33
Issue
22
fYear
1997
fDate
10/23/1997 12:00:00 AM
Firstpage
1850
Lastpage
1852
Abstract
A completion-detection technique is introduced for bundled-data asynchronous systems implemented in single-rail dynamic CMOS logic. Its application to a carry-ripple adder is presented showing significant benefits in terms of performance and area overhead
Keywords
CMOS logic circuits; adders; asynchronous circuits; bundled-data asynchronous system; carry-ripple adder; completion-detection technique; single-rail dynamic CMOS logic;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19971272
Filename
630313
Link To Document