DocumentCode
1285160
Title
High-speed CMOS frequency divider
Author
Chen, R.Y.
Author_Institution
Dept. of Electr. Eng., Nantai Inst. of Technol., Tainan, Taiwan
Volume
33
Issue
22
fYear
1997
fDate
10/23/1997 12:00:00 AM
Firstpage
1864
Lastpage
1865
Abstract
A high-speed CMOS frequency divider is proposed. Using fewer transistors and only NMOS transistors in the regenerative circuits of the latches, the frequency divider achieves higher speed through the reduced capacitances at the output nodes and larger transconductance. A device sizing rule for the maximum input frequency is given. The proposed frequency divider is suitable for high-speed operational while consuming a moderate amount of power
Keywords
CMOS analogue integrated circuits; frequency dividers; NMOS transistor; capacitance; device sizing rule; high-speed CMOS frequency divider; latch; regenerative circuit; transconductance;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19971298
Filename
630323
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