Design of a novel 12-bit 1MS/s charge redistribution SAR ADC for CZT detectors

This paper presents a novel design of a 12-bit 1MS/s SAR (Successive Approximation Register) ADC for CdZnTe (CZT) detectors application. For this SAR ADC, the main-DAC is with charge redistribution architecture to meet with low power dissipation and high speed, and the sub-DAC is a resistive divider to guarantee the linearity. To reduce the mismatches of the capacitances in the charge redistribution, a new architecture using non-lumped capacitor array is proposed, and the corresponding novel switch control algorithm is designed. The novel comparator with offset self-calibrated are proposed to improve the ADC´s accuracy. The proposed 12-bit SAR ADC is designed using TSMC 0.35um 2P4M CMOS technology. The simulation results show that, the total conversion time is about 1us, which corresponds to a sampling rate of 1MS/s. The values of the DNL and INL are -0.65~0.52LSB and -0.84~0.65LSB, respectively. The power dissipation is 3mW. The proposed ADC can be utilized in CZT detector systems which are widely used in many applications such as high-energy physics experiments, space exploration and so on.