Design of a 10-bit 50MSPS pipeline ADC for CMOS image sensor

This work describes a 10-bit 50MSPS pipeline ADC (Analog-to-Digital Converter) for CMOS (Complementary Metal Oxide Semiconductor) image sensor that is implemented in a TSMC 0.18μm CMOS process. Ten-stage pipeline architecture consists of one-stage sample-and-hold circuit, eight-stage 1.5-bit sub ADC and one-stage 2-bit flash ADC. The digital correction technique is used for calibrating the errors introduced by the comparator. A new digital correction circuit without code conversion circuit is proposed. The presented ADC operates with 3.3V power supply and achieves a power dissipation of 33 mW in typical case. Simulation results show that the values of the DNL (Differential Nonlinearity) and INL (Integral Nonlinearity) are -0.29~0.30 LSB and -0.29~0.25 LSB, respectively. The circuit achieves a SNDR (Signal-to-Noise and Distortion Ratio) of 58.28dB and a SFDR (Spurious-Free Dynamic Range) of 64.67dB with a sine wave input of 1.1 V amplitude and 4.93164 MHz frequency. The resulting FOM (Figure of Merit) is 0.984 PJ/conversion step. The proposed ADC in this paper meets the requirements of CMOS image sensor very well.