Void-effect modeling of flip-chip encapsulation on ceramic substrate

Author

Niu, Tyan-Min ; Sammakia, Bahgat G. ; Sathe, Sanjeev

Author_Institution

Div. of Microelectron., IBM Corp., Endicott, NY, USA

Volume

22

Issue

4

fYear

1999

fDate

12/1/1999 12:00:00 AM

Firstpage

484

Lastpage

487

Abstract

A detailed numerical and experimental study of the thermal-mechanical stress and strain in the solder bumps (C4s) of a flip-chip ceramic chip carrier has been completed. The numerical model used was based upon the finite element method. The model simulated accelerated thermal cycling (ATC) from 0°C to 100°C. Several parametric studies were conducted, including the effects of chip size, micro-encapsulation, and the effect of the presence of voids in the micro-encapsulant. It was notably found that the presence of voids in the encapsulant does not significantly increase the stress/strain in the C4s, with the exception of very large voids and voids at or near the edge of the chip

Keywords

ceramic packaging; encapsulation; finite element analysis; flip-chip devices; life testing; reflow soldering; thermal stresses; voids (solid); 0 to 100 degC; accelerated thermal cycling; ceramic chip carrier; chip size; finite element method; flip-chip encapsulation; micro-encapsulation; solder bumps; thermal-mechanical strain; thermal-mechanical stress; void-effect modeling; Capacitive sensors; Ceramics; Electronics packaging; Encapsulation; Fatigue; Finite element methods; Metallization; Temperature; Testing; Thermal stresses;

fLanguage

English

Journal_Title

Components and Packaging Technologies, IEEE Transactions on

Publisher

ieee

ISSN

1521-3331

Type

jour

DOI

10.1109/6144.814962

Filename

814962