DocumentCode :
1285968
Title :
Anomaly Detection and Classification for PHM of Electronics Subjected to Shock and Vibration
Author :
Lall, Pradeep ; Gupta, Prashant ; Angral, Arjun
Author_Institution :
Dept. of Mech. Eng., Auburn Univ., Auburn, AL, USA
Volume :
2
Issue :
11
fYear :
2012
Firstpage :
1902
Lastpage :
1918
Abstract :
Failures in electronics subjected to shock and vibration are typically diagnosed using the built-in self test (BIST) or using continuity monitoring of daisy-chained packages. The BIST, which is extensively used for diagnostics or identification of failure, is focused on reactive failure detection and provides limited insight into reliability and residual life. In this paper, a new technique has been developed for health monitoring and failure mode classification based on measured damage precursors. A feature extraction technique in the joint-time-frequency analysis (JTFA) domain has been developed along with pattern classifiers for fault diagnosis of electronics at the product level. The Karhunen Loéve transform (KLT) has been used for feature reduction and de-correlation of the feature vectors for fault-mode classification in electronic assemblies. Euclidean, and Mahalanobis, and Bayesian distance classifiers based on JTFA, have been used for classification of the resulting feature space. Previously, the authors have developed damage precursors based on time and spectral techniques for health monitoring of electronics without reliance on continuity data from daisy-chained packages. Statistical pattern recognition techniques based on wavelet packet energy decomposition have been studied by authors for quantification of shock damage in electronic assemblies and auto-regressive moving average; time-frequency techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems. However, identification of specific failure modes is not possible. In this paper, various fault modes, such as solder interconnect failure, interconnect missing, chip delamination, chip cracking etc., in various packaging architectures have been classified using clustering of feature vectors based on the KLT approach. The KLT de-correlates the feature space and identifies dominant directions to describe the space, el- minating directions that encode little useful information about the features. The clustered damage precursors have been correlated with underlying damage. Several chip-scale packages have been studied with lead-free second-level interconnects, including SAC105, SAC305 alloys. Transient strain has been measured during the drop event using digital image correlation and high-speed cameras operating at 100 000 frames/s. Continuity has been monitored simultaneously for failure identification. Fault-mode classification has been done using KLT and JTFA analysis of the experimental data. In addition, explicit finite element models have been developed, and various kinds of failure modes have been simulated, such as solder ball cracking, trace fracture, package falloff, and solder ball failure. Models using cohesive elements present at the solder joint-copper pad interface at both the printed circuit board and package side have also been created to study the traction-separation behavior of solder. Fault modes predicted by simulation-based precursors have been correlated with those from experimental data.
Keywords :
Bayes methods; Karhunen-Loeve transforms; assembling; autoregressive moving average processes; built-in self test; chip scale packaging; condition monitoring; copper alloys; electric shocks; failure analysis; fault diagnosis; finite element analysis; pattern classification; pattern clustering; pattern recognition; printed circuits; silver alloys; solders; statistical analysis; time-frequency analysis; tin alloys; vibrations; BIST; Bayesian distance classifiers; Euclidean distance classifiers; JTFA domain; KLT; KLT approach; Karhunen Loéve transform; Mahalanobis distance classifiers; PHM classification; SnAgCu; autoregressive moving average; built-in self test; chip cracking; chip delamination; chip-scale packages; cohesive elements; condition monitoring; daisy-chained package continuity monitoring; digital image correlation; drop event; electronic assemblies; electronic systems; electronics packaging; explicit finite element models; failure identification; failure mode classification; fault detection; fault diagnosis; feature vector clustering; feature vector decorrelation; health monitoring; high-speed cameras; interconnect missing; joint-time-frequency domainanalysis; lead-free second-level interconnects; measured damage precursors; package falloff; pattern classifiers; printed circuit board; reactive failure detection; reliability; shock damage quantification; simulation-based precursors; solder ball cracking; solder ball failure; solder interconnect failure; solder joint-copper pad interface; spectral techniques; statistical pattern recognition techniques; system identification; trace fracture; traction-separation behavior; transient strain; vibration; wavelet packet energy decomposition; Built-in self-test; Circuit faults; Electric shock; Monitoring; Strain; Time frequency analysis; Vehicles; Electronic assemblies; failure mode classification; health management; leadfree; prognostics; reliability; solder joints;
fLanguage :
English
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
2156-3950
Type :
jour
DOI :
10.1109/TCPMT.2012.2207460
Filename :
6303968
Link To Document :
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