Title :
Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs
Author :
Bulucea, Constantin ; Bahl, Sandeep R. ; French, William D. ; Yang, Jeng-Jiun ; Francis, Pascale ; Harjono, Tikno ; Krishnamurthy, Vijay ; Tao, Jon ; Parker, Courtney
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
Abstract :
The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in which the transistors for the secondary power supply voltage are offered in asymmetric and symmetric constructions. The in-depth analysis of the device physics of asymmetric transistors provides new insights into their physical operation and into the operation of transistors using halo implants in general. The variability, matching, and noise implications of using halo implants are also analyzed, concluding that both asymmetric and symmetric devices need to be offered for uncompromised circuit design. The challenges associated with the compact modeling the asymmetric transistors are also reviewed and illustrated. The preferred manufacturing implementation uses retrograde wells with no dopant fillers at the surface, while avoiding the drain-to-source punch-through by source-side-only halo implants. In addition to the known switching speed and maximum voltage gain advantages of the asymmetric transistors, this particular device architecture offers superior hot-carrier reliability and transistor design flexibility. The availability of retrograde wells enables construction of high-reliability complementary extended-drain MOSFETs for a third higher power supply voltage.
Keywords :
MOSFET; hot carriers; semiconductor device models; semiconductor device reliability; asymmetric transistors; complementary asymmetric MOSFET modelling; device architecture; halo implants; high-reliability complementary extended-drain MOSFET; hot-carrier reliability; in-depth analysis; maximum voltage gain; power supply voltage; symmetric devices; uncompromised circuit design; Circuit noise; Circuit synthesis; Implants; Integrated circuit reliability; Logic gates; MOSFETs; Physics; Power supplies; Semiconductor process modeling; Silicon; Threshold voltage; Transconductance; Virtual manufacturing; Voltage; Analog; BSIM3; CMOS; MOSFET; Medici; STI; T-gate; TSuprem-4; antipunch-through; asymmetric; compact modeling; cutoff frequency; deep and lightly doped drain extension (DLDD); doping profile; doping-gradient-induced barrier lowering (DGIBL); drain-extended MOS; drain-induced barrier lowering (DIBL); drift-diffusion; dual gate oxide (DGO); empty-well; extended-drain; extended-drain MOS (XD-MOS); gate-induced drain leakage; gate-induced source leakage (GISL); graded-channel; halo; high-voltage; hot-carrier; large-scale-integration (LSI); laterally diffused MOS (LDMOS); matching; mixed-signal; noise; output resistance; reflection coefficient; reliability; retrograde well; scattering theory; single-pocket; subcircuit; switching speed; system-on-a-chip; threshold adjust; transconductance; trench; variability; vertical diffused MOS (VDMOS); voltage gain;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2010.2057197