Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications

Author

Wang, Jinn-Shyan ; Chang, Pei-Yao ; Tang, Tai-Shin ; Chen, Jia-Wei ; Guo, Jiun-In

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Cheng Univ. (CCU), Chiayi, Taiwan

Volume

1

Issue

2

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

183

Lastpage

192

Abstract

The design of embedded subthreshold SRAMs for a quality-scalable H.264 video decoder IP is presented in this paper. In addition to the conventional 7T SRAM bitcell, we adopted power-gating techniques and multi-output dynamic circuits in order to achieve a low VDD_min, a small area overhead, and a higher operating speed. A 256 × 32 90-nm SRAM macro was designed for verifying the proposed design techniques. The H.264 IP provides energy-efficient scalable video decoding of 42.8 pJ/cycle for QCIF and 235 pJ/cycle for HD720 at 0.3 V and 0.7 V, respectively.

Keywords

SRAM chips; decoding; video coding; H.264 video decoder IP; SRAM macro; conventional 7T SRAM bitcell; embedded subthreshold SRAM; energy-efficient quality-scalable video applications; multi-output dynamic circuits; power-gating techniques; size 90 nm; voltage 0.3 V; voltage 0.7 V; Computer architecture; Decoding; Layout; Leakage current; Microprocessors; Random access memory; Simulation; H.264 decoder; SRAM; Subthreshold; embedded;

fLanguage

English

Journal_Title

Emerging and Selected Topics in Circuits and Systems, IEEE Journal on

Publisher

ieee

ISSN

2156-3357

Type

jour

DOI

10.1109/JETCAS.2011.2158345

Filename

5967919