• DocumentCode
    1286897
  • Title

    3510-V 390- \\hbox {m}\\Omega \\cdot\\hbox {cm}^{2} 4H-SiC Lateral JFET on a Semi-Insulating Substrate

  • Author

    Huang, Chih-Fang ; Kan, Cheng-Li ; Wu, Tian-Li ; Lee, Meng-Chia ; Liu, Yo-Zthu ; Lee, Kung-Yen ; Zhao, Feng

  • Author_Institution
    Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • Volume
    30
  • Issue
    9
  • fYear
    2009
  • Firstpage
    957
  • Lastpage
    959
  • Abstract
    The performance of high-voltage 4H-SiC lateral JFETs on a semi-insulating substrate is reported in this letter. The design of the voltage-supporting layers is based on the charge compensation of p- and n-type epilayers. The best measured breakdown voltage is 3510 V, which, to the authors´ knowledge, is the highest value ever reported for SiC lateral switching devices. The Ron of this device is 390 m????cm2, in which 61% is due to the drift-region resistance. The BV2/Ron is 32 MW/cm2, which is typical among other reported SiC lateral devices.
  • Keywords
    electric breakdown; junction gate field effect transistors; silicon compounds; substrates; wide band gap semiconductors; SiC; breakdown voltage; charge compensation; drift-region resistance; high-voltage lateral JFET; n-type epilayers; p-type epilayers; semiinsulating substrate; voltage 3510 V; voltage-supporting layers; High voltage; JFETs; lateral; silicon carbide;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2009.2027722
  • Filename
    5191105
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1286897