DocumentCode :
1287318
Title :
Gated-four-probe a-Si:H TFT structure: a new technique to measure the intrinsic performance of a-Si:H TFT
Author :
Chen, Chun-ying ; Kanicki, Jerzy
Author_Institution :
Dept. of Electr. Eng., Michigan Univ., Ann Arbor, MI, USA
Volume :
18
Issue :
7
fYear :
1997
fDate :
7/1/1997 12:00:00 AM
Firstpage :
340
Lastpage :
342
Abstract :
In this letter, a new technique based on gated-four-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series resistances.
Keywords :
amorphous semiconductors; elemental semiconductors; hydrogen; silicon; thin film transistors; Si:H; drain-source current; field-effect conductance activation energy; gated-four-probe a-Si:H TFT; hydrogenated amorphous silicon thin-film transistor; intrinsic performance measurement; mobility; source/drain series resistance; threshold voltage; voltage difference; Amorphous silicon; Computer displays; Electrical resistance measurement; Equations; Least squares methods; Probes; Thin film transistors; Threshold voltage; Voltage measurement;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/55.596930
Filename :
596930
Link To Document :
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