Transistor variability after CHC and NBTI stress in 90 nm pMOSFET technology

An investigation is conducted of mismatching properties after channel hot carrier (CHC) and negative bias temperature instability (NBTI) stress is observed using pMOSFETs of various device sizes from 90 nm CMOS technology. The purpose of this study is to analyse the mismatching of transistor pairs after the foregoing reliability tests. Degradations of the pMOSFETs are extracted by measuring variations of Vtlin and Idsat before and after stress. The experiments show that CHC mode is more serious than that of NBTI mode. The probable mechanism of the transistor mismatches is due to the random generation traps in the gate dielectric (SiON) and at the interface between SiON/Si-bulk. Furthermore, the results suggest that CHC involves the integration of HC and NBTI effects induced transistor mismatches, particularly for small size devices.