Novel Layout Technique for N-Hit Single-Event Transient Mitigation via Source-Extension

In this paper, a novel layout technique for N-hit single-event transient (SET) mitigation that is based on source-extension is proposed. Based on 65 nm bulk CMOS technology, both mixed-mode numerical simulations with technology computer-aided design (TCAD), as well as heavy-ion experiments show SET pulse widths are efficiently reduced with source extension. As opposed to what is found in the P-hit SET production process, where the source plays a detrimental role in SET mitigation due to the well-known bipolar effect, in the N-hit SET production process the source plays a beneficial role in reducing SET pulse widths, attributable to a parasitic reversed bipolar effect. This effect will be discussed in depth in this paper, and the proposed ´radiation hardened by design´ (RHBD) layout technique will be extended to common combinational standard cells. The area penalty will also be discussed for the proposed layout technique. Meanwhile, both the P-hit and N-hit SET mitigation layout techniques will be introduced into the standard inverter layout, and the final improvement in SET pulse width will be discussed.