Title :
Efficient delay yield estimate of digital circuits
Author :
Jiang, X.H. ; Allan, G.A.
Author_Institution :
Dept. of Electron. & Electr. Eng., Edinburgh Univ., UK
fDate :
11/25/1999 12:00:00 AM
Abstract :
A theoretical approach is presented for accurately estimating the delay yield of CMOS digital circuits when inter-die and intra-die variations are considered. Where this estimate is required to be of greater accuracy, a criterion is presented to determine the minimum number of paths that should be analysed by Monte Carlo simulation to achieve the required accuracy
Keywords :
CMOS digital integrated circuits; Monte Carlo methods; circuit simulation; delay estimation; integrated circuit design; integrated circuit yield; CMOS digital circuits; Monte Carlo simulation; delay yield estimate; digital circuits; inter-die variations; intra-die variations; minimum path number;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991416
