Title :
Verilog-A compact model for oxide-based resistive random access memory (RRAM)
Author :
Zizhen Jiang ; Shimeng Yu ; Yi Wu ; Engel, Jesse H. ; Ximeng Guan ; Wong, H.-S Philip
Author_Institution :
Center for Integrated Syst. & Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.
Keywords :
hardware description languages; random-access storage; real-time systems; dynamic Verilog-A RRAM compact model; oxide-based resistive random access memory; pulse parameter fitting methodology; pulsed operation device behavior; random variability; real-time DC cycling; Fitting; Hardware design languages; Integrated circuit modeling; Mathematical model; Resistance; Switches; Compact model; RRAM; Verilog-A; variations;
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2014 International Conference on
Conference_Location :
Yokohama
Print_ISBN :
978-1-4799-5287-8
DOI :
10.1109/SISPAD.2014.6931558
