Title :
Design and Analysis of a 77.3% Locking-Range Divide-by-4 Frequency Divider
Author :
Kuo, Yen-Hung ; Tsai, Jeng-Han ; Chang, Hong-Yeh ; Huang, Tian-Wei
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A cascoded frequency divider (FD) with division number of 4 and ultra-wide locking range is presented in this paper. The proposed FD consists of a divide-by-2 (D2) injection-locked frequency divider (ILFD) core and a D2 source-injection current mode logic (SICML) divider. After the cascoded integration of ILFD and SICML, the removal of transconductance and buffer stages can lower the dc power consumption and widen the locking range. The proposed FD is implemented in 0.13-μm CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power. Compared to the previously reported ILFDs, the proposed circuit achieves the widest locking range without employing extra tuning mechanism.
Keywords :
CMOS logic circuits; current-mode logic; field effect MIMIC; field effect MMIC; frequency dividers; integrated circuit design; low-power electronics; CMOS technology; ILFD core; SICML divider; cascoded frequency divider; dc power consumption; divide-by-2 injection-locked frequency divider core; divide-by-2 source-injection current mode logic divider; frequency 13.5 GHz to 30.5 GHz; locking-range divide-by-4 frequency divider design; power 7.3 mW; size 0.13 mum; ultra-wide locking range; Bandwidth; Harmonic analysis; Latches; Mixers; Phase locked loops; Topology; CMOS; current mode logic (CML) latch; divide-by-4 (D4); injection-locked frequency divider (ILFD); monolithic microwave integrated circuit (MMIC); phase-locked loop (PLL); wide locking range;
Journal_Title :
Microwave Theory and Techniques, IEEE Transactions on
DOI :
10.1109/TMTT.2011.2160963
