Title :
Physical Model for the Small-Scale Residual Topography in Chemical Mechanical Polishing
Author :
Urbach, Jan-Peter
Author_Institution :
Dept. of Comput.-Aided Design, Qimonda, Munich, Germany
Abstract :
In previous work, the small-scale topography evolution of the wafer surface was investigated for a typical interlevel dielectric chemical mechanical planarization process by means of a Fourier analysis of surface profiler scans. It was found that the amplitudes of the individual frequency components decay exponentially at a rate that depends on the respective spatial frequency. In this paper, a physical model of these findings is proposed, based on a linearized approximation of the Greenwood-Williamson approach to describe the contact between the pad and the wafer surface. The frequency dependency of the decay rates is attributed to the visco-elastic properties of the pad material (polyurethane). This connection is consistent with dielectric susceptibility measurements that show that the observed frequency dependency stems from a visco-elastic beta-transition in polyurethane. The resulting model not only describes the experimental data for a previous test pattern but also shows good agreement to measurements of a typical dynamic random access memory topography after chemical mechanical polishing. In addition, the current model reduces the systematic errors of the predicted topography as compared to the previous empirical model.
Keywords :
Fourier analysis; chemical mechanical polishing; optical susceptibility; semiconductor process modelling; viscoelasticity; Fourier analysis; Greenwood-Williamson approach; decay rates; dielectric susceptibility; interlevel dielectric chemical mechanical planarization; linearized approximation; polyurethane pad material; small-scale residual topography; surface profiler scans; viscoelastic beta-transition; wafer surface; Frequency measurement; Linear approximation; Planarization; Semiconductor device modeling; Surface topography; Semiconductor process modeling;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
DOI :
10.1109/TSM.2011.2163429