DocumentCode :
128865
Title :
Implementation issues in the hierarchical composition of performance models of analog circuits
Author :
Velasco-Jimenez, M. ; Castro-Lopez, R. ; Roca, E. ; Fernandez, F.V.
Author_Institution :
Inst. de Microelectron. de Sevilla, Univ. de Sevilla, Sevilla, Spain
fYear :
2014
fDate :
24-28 March 2014
Firstpage :
1
Lastpage :
6
Abstract :
Emerging hierarchical design methodologies based on the use of Pareto-optimal fronts (PoFs) are promising candidates to reduce the bottleneck in the design of analog circuits. However, little work has been reported about how to transmit the information provided by the PoFs of low hierarchical level blocks through the hierarchy to compose the performance models of higher-level blocks. This composition actually poses several problems such as the dependence of the PoF performances on the surrounding circuitry and the complexity of dealing with multi-dimensional PoFs in order to explore more efficiently the design space. To deal with these problems, this paper proposes new mechanisms to represent and select candidate solutions from multi-dimensional PoFs that are transformed to the changing operating conditions enforced by the surrounding circuitry. These mechanisms are demonstrated with the generation of the performance model of an active filter by composing previously generated PoFs of operational amplifiers.
Keywords :
Pareto analysis; analogue circuits; evolutionary computation; Pareto optimal fronts; active filter; analog circuits; hierarchical design methodologies; higher level blocks; low hierarchical level blocks; operational amplifiers; Design methodology; Indexing; Loading; Optimization; Sociology; Statistics; Transistors; Hierarchical design methodologies; Pareto-optimal fronts; evolutionary algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location :
Dresden
Type :
conf
DOI :
10.7873/DATE.2014.025
Filename :
6800226
Link To Document :
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