Title :
Nano-meter scaled gate area high-K dielectrics with trap-assisted tunneling and random telegraph noise
Author :
Lin, Po-Jui Jerry ; Lee, Zhe-An Andy ; Yao, Chih-Wei Kira ; Lin, Hsin-Jyun Vincent ; Watanabe, Hiromi
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
If the trap density is 1012 cm-2, then there are only one trap in 10nm × 10nm on average. Accordingly, three-dimensional simulation that is sensitive to the movement of sole electron is indispensable for carefully investigating the reliability issues related to local traps in future nano-electron devices. As a demonstration, we investigate Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT) at the same moment in 5nm×5nm gate area high-K dielectrics (EOT= 0.8nm to 0.47nm). The simulation is carried out with respect to various gate biases, physical thickness of high-K, interlayer suboxide thickness, and dielectric constant of high-K. It is suggested that thinner suboxide and higher permittivity can suppress the increase of the leakage current which is caused by TAT.
Keywords :
electron traps; high-k dielectric thin films; leakage currents; nanostructured materials; permittivity; random noise; reliability; tunnelling; 3D simulation; RTN; TAT; dielectric constant; electron movement; gate biases; high-K dielectrics; interlayer suboxide thickness; leakage current; local traps; nanoelectron devices; nanometer scaled gate area; permittivity; physical thickness; random telegraph noise; reliability; trap density; trap-assisted tunneling; Electric potential; Electron traps; High K dielectric materials; Logic gates; Silicon; Substrates; Tunneling; high-K dielectrics; interlayer suboxide; random telegraph noise; simulation; single-electron; trap-assisted tunneling;
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2014 International Conference on
Conference_Location :
Yokohama
Print_ISBN :
978-1-4799-5287-8
DOI :
10.1109/SISPAD.2014.6931608
