DocumentCode :
1289103
Title :
Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique
Author :
Morifuji, Eiji ; Aikawa, Hisashi ; Yoshimura, Hisao ; Sakata, Akio ; Ohta, Masako ; Iwai, Masaaki ; Matsuoka, Fumitomo
Author_Institution :
Syst. LSI Div., Toshiba Corp., Kawasaki, Japan
Volume :
56
Issue :
9
fYear :
2009
Firstpage :
1991
Lastpage :
1998
Abstract :
Layout dependences for stress-enhanced MOSFETs including contact positioning, the second neighboring poly effect, and bent diffusion are modeled in 45-nm CMOS logic technology. It is found that the sensitivity of contact position in the channel direction is larger for PMOS with a higher stress liner than for NMOS. The effect of contact positions is modeled by using the distance of contact to gate (x) and the number of contacts (N). In terms of the gate-space effect, it is concluded that, in addition to the neighboring gates, second neighboring gates affect the channel stress. The effect of bent-shape diffusion is analyzed for NMOS and PMOS. For NMOS, the channel profile is affected by the bent shape. This can be described by the change of V th. For PMOS, the channel stress is modulated by the bent diffusion. The stress effect in bent-shape diffusion for PMOS is modeled with three geometrical parameters. The compact model is applied to the characterization of actual 45-nm cell libraries. It is confirmed that, with the constructed models and design flow, a saturation current (I dsat) change of -12%-14% is removed from the uncertain margin in 45-nm corner libraries.
Keywords :
CMOS digital integrated circuits; MOSFET; integrated circuit layout; CMOS logic technology; MOSFET; NMOS; PMOS; bent diffusion; bent shape diffusion; channel profile; channel stress; complementary metal-oxide-semiconductor integrated circuits; contact positioning; gate-space effect; layout dependence modeling; metal-oxide-semiconductor field effect transistors; size 45 nm; stress effect; stress-enhanced technique; CMOS logic circuits; CMOS technology; Germanium silicon alloys; MOS devices; MOSFET circuits; Semiconductor device modeling; Shape; Silicon germanium; Software libraries; Stress; CMOS digital integrated circuits; CMOSFET logic devices; SPICE; integrated circuit layout; stress;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2009.2026121
Filename :
5196785
Link To Document :
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