The importance of the internal bulk-source potential on the low temperature kink in NMOSTs

Author

Deferm, Ludo ; Simoen, E. ; Claeys, Cor

Author_Institution

IMEC, Leuven, Belgium

Volume

38

Issue

6

fYear

1991

fDate

6/1/1991 12:00:00 AM

Firstpage

1459

Lastpage

1466

Abstract

The kink occurring at low temperatures in the I_DS-V_DS curves of NMOS transistors is explained by the direct correlation between the current injected into the source, the internal bulk potential, and the resulting change in threshold voltage. A semi-two-dimensional analytical model is derived for calculating the influence of the multiplication current from room temperature down to liquid-helium temperature. Only steady-state equations are derived and no time effects are included. The proposed model gives the possibility of quite accurately calculating the influence of the device geometry. Extension to the case of silicon-on-insulator (SOI) transistors is also briefly discussed

Keywords

insulated gate field effect transistors; semiconductor device models; 2D model; 300 to 4.2 K; NMOS transistors; SOI transistors; Si; bulk transistors; change in threshold voltage; device geometry; internal bulk-source potential; low temperature kink; multiplication current; room temperature; steady-state equations; Analytical models; Bipolar transistors; CMOS technology; Cryogenics; Geometry; Helium; Impedance; MOSFETs; Temperature; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.81639

Filename

81639