Soft error protection using asymmetric response latches

A static latch design is analyzed whose single event upset (SEU) sensitivity is extremely dependent on its logic state. The authors employ a modification of a hardened static memory cell to construct an asymmetrical latch. Both the original and asymmetric latches are illustrated. The original idea was that resistors in the drain lines provide voltage division at the feedback point for p-drain strikes (or voltage transients). Proper choice of the resistor value relative to the on resistance of the n-channel transistor will insure that the feedback voltage can never reach the switch point of the opposite inverter, preventing cell upset for any p-drain transient. Such latches respond symmetrically with respect to logic state, displaying essential immunity to one SEU mechanism. A simple AND gate for two of these asymmetric response latches provides high-speed error correction for a single bit, and the combination represents a hardened logic element