Title :
Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology
Author :
Flandre, Denis ; Viviani, Alberto ; Eggermont, Jean-Paul ; Gentinne, Bernard ; Jespers, P.G.A.
Author_Institution :
Lab. de Microelectron., Univ. Catholique de Louvain, Belgium
fDate :
7/1/1997 12:00:00 AM
Abstract :
A systematic study of the gain-boosted regulated-cascode operational transconductance amplifier (OTA) CMOS stage is presented. Symbolic analysis is used first to describe the pole-zero behaviour and second to propose design criteria for optimal settling time. A synthesis procedure based on the “gm/ID” methodology is considered further on for quick optimization of the architecture based on the dc open-loop gain, transition frequency, and settling time specifications. Practical design cases are finally discussed
Keywords :
CMOS analogue integrated circuits; integrated circuit design; operational amplifiers; poles and zeros; symbol manipulation; DC open-loop gain; design; gain-boosted regulated-cascode CMOS stage; gm/ID methodology; operational transconductance amplifier; optimization; pole-zero analysis; settling time; symbolic analysis; synthesis; transition frequency; CMOS analog integrated circuits; Circuit stability; Circuit synthesis; Design optimization; Frequency synthesizers; Integrated circuit synthesis; Operational amplifiers; Optimization methods; Transconductance; Transient response;
Journal_Title :
Solid-State Circuits, IEEE Journal of
