Distributed generation of weighted random patterns

Author

Savir, Jacob

Author_Institution

Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

Volume

48

Issue

12

fYear

1999

fDate

12/1/1999 12:00:00 AM

Firstpage

1364

Lastpage

1368

Abstract

This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to “go after” the remaining untested faults. The cost and performance of this design system are explored on ten pilot chips. Results of this experiment are provided in the paper

Keywords

built-in self test; logic testing; LSSD SRLs; distributed generation; distributed weighted pattern test approach; two-bit code; weighted random patterns; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Distributed control; Electrical fault detection; Fault detection; Jacobian matrices; Signal detection;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.817399

Filename

817399