Title :
IC test structures for multilayer interconnect stress determination
Author :
Smee, Stephen A. ; Gaitan, Michael ; Novotny, Donald B. ; Joshi, Yogendra ; Blackburn, David L.
Author_Institution :
Dept. of Mech. Eng., Maryland Univ., College Park, MD, USA
Abstract :
A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures. Stress values, calculated from constitutive relations, are in good agreement with published results.
Keywords :
CMOS integrated circuits; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; internal stresses; thermal stresses; IC test structures; MEMS-based test structures; constitutive relations; dual-metal-layer CMOS process; interconnect stress determination; longitudinal interconnect stress; multilayer interconnect; strain measurements; CMOS process; Circuit testing; Dielectric measurements; Integrated circuit interconnections; Integrated circuit testing; Micromechanical devices; Nonhomogeneous media; Strain measurement; Stress measurement; Thermal stresses;
Journal_Title :
Electron Device Letters, IEEE
