Title :
Package clock distribution design optimization for high-speed and low-power VLSIs
Author :
Zhu, Qing ; Tam, Simon
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fDate :
2/1/1997 12:00:00 AM
Abstract :
With continually increased difficulties of the clock distribution in high speed microprocessors and application-specific integrated circuits (ASICs), the package clock distribution shows very promising advantages. The concurrent design of chip and package will provide the optimal design of a clock network by taking the advantages of package layers. The package layers provide 1000 times less wire resistance and 10 times less wire capacitance than those of interconnects on chip. Therefore, it is more beneficial to route the global clock network on package. The implementation issues of the package clock distribution are described in this paper, including the electrostatic discharge (ESD) circuit design for local clock buffers and transmission line noise suppression for package clock trees
Keywords :
VLSI; application specific integrated circuits; circuit optimisation; electrostatic discharge; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; microprocessor chips; network routing; protection; timing circuits; ASIC; ESD circuit design; application-specific integrated circuits; concurrent design; design optimization; electrostatic discharge; global clock network routing; high speed microprocessors; high-speed VLSI; local clock buffers; low-power VLSI; package clock distribution; package clock trees; transmission line noise suppression; Application specific integrated circuits; Capacitance; Circuit synthesis; Clocks; Design optimization; Electrostatic discharge; Integrated circuit interconnections; Integrated circuit packaging; Microprocessors; Wire;
Journal_Title :
Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on
