DocumentCode :
129079
Title :
Efficient SMT-based ATPG for interconnect open defects
Author :
Erb, Dominik ; Scheibler, Karsten ; Sauer, Matthias ; Becker, B.
Author_Institution :
Univ. of Freiburg, Freiburg, Germany
fYear :
2014
fDate :
24-28 March 2014
Firstpage :
1
Lastpage :
6
Abstract :
Interconnect opens are known to be one of the predominant defects in nanoscale technologies. However, automatic test pattern generation for open faults is challenging, because of their rather unstable behaviour and the numerous electric parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints and use simplified fault models in order to detect as many faults as possible or make assumptions which decrease both complexity and accuracy. This paper presents a new SMT-based approach which for the first time supports the Robust Enhanced Aggressor Victim model without restrictions and handles oscillations. It is combined with the first open fault simulator fully supporting the Robust Enhanced Aggressor Victim model and thereby accurately considering unknown values. Experimental results show the high efficiency of the new method outperforming previous approaches by up to two orders of magnitude.
Keywords :
automatic test pattern generation; integrated circuit interconnections; integrated circuit testing; nanoelectronics; SAT modulo theory; SMT-based ATPG; automatic test pattern generation; interconnect open defects; nanoscale technologies; robust enhanced aggressor victim model; Automatic test pattern generation; Capacitance; Circuit faults; Couplings; Integrated circuit interconnections; Integrated circuit modeling; Logic gates; ATPG; Interconnect opens; SMT; test generation; unknown values;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
Conference_Location :
Dresden
Type :
conf
DOI :
10.7873/DATE.2014.138
Filename :
6800339
Link To Document :
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