An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

Author

Hegong Wei ; Chi-Hang Chan ; U-Fat Chio ; Sai-Weng Sin ; Seng-Pan U ; Martins, Rui P. ; Maloberti, Franco

Author_Institution

State Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China

Volume

47

Issue

11

fYear

2012

Firstpage

2763

Lastpage

2772

Abstract

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FOM is 73 fJ/conversion-step at 400 MS/s from 1.2-V supply and 42 fJ/conversion-step at 250 MS/s from a 1-V supply. The active area with the digital calibration is 0.028 mm².

Keywords

CMOS integrated circuits; analogue-digital conversion; digital-analogue conversion; 2-b-per-cycle SAR ADC; 8-b-per-cycle SAR ADC; CMOS low-power; SFDR; SNDR; analog-to-digital converter; highly integrated circuit implementation; rapid conversion rate; resistive DAC; successive approximation register; wavelength 65 nm; Calibration; Capacitance; Clocks; Decoding; Interpolation; Registers; Switches; 2-b-per-cycle (2 b/C); Analog-to-digital converter (ADC); resistive DAC; successive approximation register (SAR);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2012.2214181

Filename

6311441