Title :
All-Digital Frequency Synthesizer Using a Flying Adder
Author :
Sung, Gang-Neng ; Liao, Szu-Chia ; Huang, Jian-Ming ; Lu, Yu-Cheng ; Wang, Chua-Chin
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
This brief presents an all-digital frequency synthesizer based on the flying adder (FA) architecture. The FA is a fascinating architecture for frequency synthesizer designs due to its simplicity and effectiveness. The FA-based frequency synthesizer can simply use a set of multiple phase reference signals to generate a desired frequency to achieve fast frequency switching. In the proposed work, the frequency synthesizer adopts an all-digital phase-locked loop to provide a steady reference signal for the FA. The proposed frequency synthesizer is implemented in a standard 0.18-μm CMOS cell-based technology, and the core area is 0.16 mm2. The output frequency range is 39.38-226 MHz, and the peak-to-peak jitter is less than 130 ps.
Keywords :
CMOS integrated circuits; adders; digital phase locked loops; frequency synthesizers; CMOS cell-based technology; all-digital frequency synthesizer; all-digital phase-locked loop; flying adder; frequency 39.38 MHz to 226 MHz; multiple phase reference signals; size 0.18 mum; Adders; Clocks; Delay; Frequency control; Frequency synthesizers; Phase locked loops; Switches; All-digital frequency synthesizer (ADFS); CMOS; all-digital phase-locked loop (ADPLL); flying adder (FA); low power;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2010.2056011