Zero-crossing DPLL bit synchronizer with pattern jitter compensation

A digital phase-locked loop (DPLL) bit synchronizer that tracks the zero crossings of a bandlimited binary signal is discussed. The synchronizer reduces pattern jitter or self noise with a compensation signal in the synchronizer feedback loop without using a prefilter. Analytical results are derived for the timing jitter variance (additive noise and self noise) of the synchronizer. Computer simulations and laboratory measurements are shown to verify the effectiveness of the pattern jitter compensation techinque for a synchronizer operating with both spectral raised cosine signaling pulses as well as for signaling pulses generated by a realizable filter network. Implementation of the pattern jitter compensation method in an adaptive synchronizer structure for applications where a priori knowledge of the signaling pulse shape is not available is also discussed