Interconnect scaling scenario using a chip level interconnect model

Author

Yamashita, Kyoji ; Odanaka, Shinji

Author_Institution

ULSI Process Technol. Center, Matsushita Electron. Corp., Kyoto, Japan

Volume

47

Issue

1

fYear

2000

fDate

1/1/2000 12:00:00 AM

Firstpage

90

Lastpage

96

Abstract

This paper describes an interconnect scaling scenario, which considers the impact of metal aspect ratio and pitch at each layer, new interconnect materials, and improved circuit design techniques. A new design methodology for a multilevel interconnect scheme is proposed on the basis of a chip level interconnect model. The design rule, the number of metal layers, and selection of interconnect materials at each device generation are projected using this methodology. It is shown that the 0.13-μm CMOS generation requires not only new interconnect materials but also improved circuit design techniques such as variable pitch router and insertion of repeater buffers. A high-performance LSI in the 0.13-μm CMOS generation needs seven layers using Cu interconnect and low-k dielectrics

Keywords

CMOS integrated circuits; copper; integrated circuit design; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; large scale integration; 0.13 micron; CMOS IC design; Cu; Cu interconnect; chip level interconnect model; circuit design techniques; deep submicron CMOS; design methodology; design rule; high-performance LSI; interconnect materials; interconnect scaling scenario; low-k dielectrics; metal aspect ratio; metal pitch; multilevel interconnect scheme; repeater buffers insertion; variable pitch router; CMOS technology; Capacitance; Circuit synthesis; Delay; Design methodology; Integrated circuit interconnections; Large scale integration; Semiconductor device modeling; Stochastic processes; Wiring;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.817572

Filename

817572